Makefile && Gcc

Passando argumento para o Makefile
Exemplo

"Makefile"
...
# Variavel
ARGUMENTO := '10'
./meuprograma $(ARGUMENTO)

...

# make
> ./meuprograma
# make ARGUMENTO=20
> ./meuprograma 20

**************************************************************************

Passando argumento para o gcc

"olamundo.c"
..
#include
int main(){
#if OLA==1
printf(MENSAGEM);
#endif
return 0;
}
..
# gcc teste.c -DOLA=1 -DMENSAGEM="\"Ola mundo cruel\"" -o teste
# ./teste
> Ola mundo cruel
# gcc teste.c -DOLA=2 -DMENSAGEM="\"Ola mundo cruel\"" -o teste
>

*************************************************************************
Exemplo de Makefile simplificado usando macros

CSOURCES = $(wildcard *.c)
CFLAGS = -lpthread -lncurses

all: rollercoaster

rollercoaster: $(CSOURCES:.c=.o)
@echo Compilando o programa final "["$@"]" , "["$^"]"
@gcc -o $@ $^ $(CFLAGS)

%.o: %.c
@echo Compilando arquivo objeto: $@
@gcc -c $< -o $@

clean:
@echo Limpando arquivos
@rm -f *.o *~ rollercoaster


# ####################################################
# Makefile do Hello World usado no ArchC
# ####################################################

CC = mips-elf-gcc
CFLAGS = -msoft-float -specs=archc
LDFLAGS = -lm

TARGET = teste.x
INC_DIR := -I.

SRCS := teste.c
OBJS := $(SRCS:.c=.o)

#------------------------------------------------------
.SILENT:

#------------------------------------------------------
.SUFFIXES: .o .c .h

#------------------------------------------------------
all: $(OBJS)
$(CC) $(OBJS) $(CFLAGS) -o $(TARGET) $(LDFLAGS)
#------------------------------------------------------
clean:
rm -f *.o *~ $(TARGET)
#------------------------------------------------------
.c.o:
$(CC) -c $(CFLAGS) $(INC_DIR) -c $